Via Current Capacity Calculator

How is PCB via current capacity determined?

A PCB via is a plated-through hole that connects traces across board layers. Its current capacity depends on the cross-sectional area of the copper plating, which forms a hollow cylinder inside the drilled hole. This calculator applies the IPC-2221 conductor formula with the external-layer constant to that copper ring — the common convention for vias; IPC-2152 gives more detailed thermal guidance.

The effective conductor area of a via is the annular ring of plating: A = π × t_plating × (D_hole + t_plating), where D_hole is the finished hole diameter and t_plating is the electroplated copper thickness (typically 18–25 μm for standard PCBs). This area is significantly smaller than an equivalent-width surface trace.

Via resistance is calculated from the plating cross-section and via length (board thickness). For high-current paths, multiple vias in parallel are used to increase total cross-section. Thermal vias—arrays of small vias connecting to internal copper planes—also serve as heat conduits for power components.

Formula: A = π × t_plating × (D_hole + t_plating) R_via = ρ_Cu × L / A I_max ≈ k × ΔT^0.44 × A^0.725 P_dissipated = I² × R_via

Example Calculation

A via with 0.3 mm hole diameter, 25 μm plating, and 1.6 mm board thickness: A = π × 0.025 × (0.3 + 0.025) = 0.0255 mm². R = 1.724×10⁻⁵ × 1.6 / 0.0255 = 1.08 mΩ. At 1A, power dissipation = 1² × 0.00108 = 1.08 mW.

When to Use This Calculator

• Determining how many parallel vias are needed for a high-current power connection between PCB layers
• Evaluating whether a single via is sufficient for a signal transition or if it creates a current bottleneck
• Designing thermal via arrays under power components (QFN, LGA) to determine the number and size of vias for adequate heat dissipation
• Calculating via resistance contribution to a power delivery network (PDN) to maintain target impedance

Common Mistakes to Avoid

• Assuming the via hole is filled with copper — standard plated-through vias have a hollow copper cylinder, not a solid conductor; the cross-sectional area is the annular ring, not the full hole area
• Using nominal plating thickness without verifying actual fabrication capability — minimum plating thickness can be as low as 18 μm even when the nominal spec says 25 μm, reducing current capacity by 28%
• Placing too few vias for high-current paths and creating thermal hot spots — a single via carrying 2A can heat locally to 30-50°C above ambient
• Ignoring via aspect ratio limitations — board thickness divided by drill diameter should not exceed 10:1 for standard processes, or plating uniformity degrades

How to Interpret Results

• Via current capacity scales with the copper-ring cross-section (plating thickness around the barrel), not with the hole diameter alone — thicker plating carries more current.
• The result is for a single via; for high-current nets use several vias in parallel to divide both the current and the thermal load.
• Thermal resistance indicates how well the via conducts heat between layers — thermal-via arrays under power devices rely on low per-via thermal resistance.
• Typical plated barrels are ~20–30 µm thick; if your fabricator plates thinner, the real capacity is lower than the calculated value.

Related Standards & References

• IPC-2152 — Standard for determining current-carrying capacity in printed board design, including via analysis
• IPC-6012 — Qualification and performance specification for rigid printed boards, defining plating thickness requirements
• IPC-2221 — Generic standard on printed board design, providing baseline via design guidelines

Frequently Asked Questions

How many vias are needed for a high-current connection?

A single standard via (0.3 mm drill, 25 μm plating) can typically handle 0.5–1.5A depending on acceptable temperature rise. For higher currents, use multiple vias in parallel—each via adds its cross-section to the total. For example, a 5A connection might require 4–6 standard vias. Place them close together to minimize trace length between vias.

What is the difference between via current capacity per IPC-2221 and IPC-2152?

IPC-2221 has no via-specific chart; the common convention, used here, applies its empirical conductor formula to the barrel cross-section with the external-layer constant. IPC-2152 provides more detailed thermal analysis considering board stackup, copper plane proximity, and via aspect ratio. IPC-2152 generally yields higher allowable currents for vias near large copper planes due to better heat spreading, giving more realistic results for modern multilayer PCBs.

Can thermal vias be used for both heat dissipation and electrical current?

Yes, thermal vias serve a dual purpose. When placed under a power component's thermal pad, they conduct both heat to internal copper planes and electrical current to the ground or power plane. For optimal performance, use the largest practical drill size (0.3-0.5 mm), ensure full copper plating (no tenting), and place vias in a tight array to maximize total thermal and electrical conductance.